1. Field of the Invention
The present invention relates generally to dead-time compensation of solid-state power switch components in electronic devices such as inverters and converters. Specifically, the preferred embodiments of the present invention relate to means that compensate the voltage distortion and minimize the available voltage range loss of electronic devices both caused by switching dead-time of solid-state power switches in such devices.
2. Description of the Related Art
In modern power inverter/converter technology, a switching power device, such as an insulated gate bipolar transistor (IGBT), is often utilized to convert direct-current (DC) power into alternating-current (AC) power and pulse width modulated (PWM) method is widely adopted in switching pattern control. FIG. 1A shows part of a one-phase configuration of a DC-to-AC power converter (inverter) 100. Although not shown in the figure, it should be understood by those skilled in the art that the current Ia is going out to a load having one end connected to node a; with the other end of the load connected to another pair of transistors and diodes that are arranged in a similar manner to solid-state power switch components 110, 130 and diodes 120, 140. The switches 110 and 130 can be any solid-state transistors, such as IGBTs.
In a power conversion application such as shown in FIG. 1A one of the big concerns is the harmonic voltage generated from the inverter 100. The harmonic voltage is caused by the non-linearity behaviors of the switching operation of the inverter 100. A major non-linearity is introduced by the dead-time required for the solid-state power switches 110 and 130. This is because it is well known that there is no ideal switching component that can turn on and turn off instantaneously. To guarantee that both switches 110 and 130 in an inverter such as the one shown in FIG. 1A never conduct simultaneously a small blanking time, conventionally called dead-time, is inserted between the gate signals of the turning-off and turning-on switches to avoid a so-called shoot-through of the DC power source. This dead-time is used to delay for a short period of time for the coming-on switch to be turned on from the moment when the coming-off switch is turned off (i.e., when the falling edge of the coming-off switch occurs). FIG. 1B shows the dead-time between the off edge of the switch or IGBT 130 and the on edge of the switch or IGBT 110. FIG. 1C shows the inverter output voltage Van in a PWM cycle with gate drive signal as in FIG. 1B at the conditions of output current Iaxe2x89xa70 and Ia less than 0. Because of the dead time shown in FIG. 1B, a voltage waveform distortion is induced as shown in FIG. 2. In the figure, curve 211 shows the average output voltage waveform from an inverter, such as inverter 100 shown in FIG. 1A, with ideal switching components having no dead-time requirement. As a result, the curve 211 has a very good sinusoidal waveform. Curve 212, however, shows the average output voltage from an inverter with dead time added as required for actual switching components. As seen, curve 212 is severely distorted around the zero crossing (of the phase current Ia shown by curve 213) when compared to the ideal sinusoidal waveform of curve 211. Curve 212 also shows that the inverter output AC voltage is lower than the nominal voltage (of ideal curv 211) in the half cycle corresponding to positive half cycle of current Ia shown in curve 213; whereas, the inverter output AC voltage is higher than the nominal voltage in the voltage half cycle corresponding to negative half cycle of the phase current Ia. Due to the dead-time effect, the voltage distortion becomes more severe at the point of current polarity change, i.e., zero crossing.
The voltage loss (or gain) between the nominal or ideal voltage curve 211 and the distorted voltage curve 212 in FIG. 2 can be compensated by a compensation voltage waveform as shown by Curve 214. The compensation voltage 214 is the amount of voltage loss, as defined by the difference between the nominal voltage 211 and the distorted voltage 212. However, the attention should not only be put to the exact amount of voltage loss compensation but also to the right moment of the compensation. FIG. 3 shows the inverter voltage distortion with correct voltage amount compensation but not at the right moment. Again, curve 311 is a copy of the phase current Ia waveform 213 shown in FIG. 2. Curve 312 is a copy of the distorted voltage waveform 212 shown in FIG. 2 without any dead-time compensation. Curve 313 is a copy of the compensation voltage 214 shown in FIG. 2. Curve 314 shows the resulting voltage waveform which is even more distorted than the distorted voltage waveform 212 because the compensation was not done at the right moment. For a three-phase inverter with three legs, each as shown in FIG. 1A, the voltage distortions as shown in curve 212 of FIG. 2 and curve 314 in FIG. 3 will generate severe 5th and 7th harmonics that will deteriorate the power quality for a three phase power system.
Besides the voltage distortion effect, the dead-time has another negative impact on the performance of the inverter 100. This dead-time takes part of a PWM cycle time and reduces the portion in a PWM cycle used to control IGBT""s on or off time. In other words, when the dead time in a PWM cycle gets larger, the available time range for IGBT""s on or off gets smaller, and a smaller output voltage range can be obtained from the inverter 100 with certain DC voltage. This dead-time effect is illustrated in FIGS. 1B and 1C. As shown in FIG. 1C, because of the dead time effect, Van when Iaxe2x89xa70 has a smaller voltage width than Van when Ia less than 0. Thus, the average voltage magnitude of Van when Iaxe2x89xa70 is less than the average voltage magnitude of Van when Ia less than 0. The following example is used to further explain this dead time effect.
Let""s assume the inverter PWM cycle is 100 xcexcs (microseconds) and the maximum or nominal AC output voltage from the inverter with 0 xcexcs dead-time is 1.0. Table 1 shows the maximum inverter output voltages when various amounts of dead time is added.
For instance, when the added dead time is 2.0 xcexcs, the actual amount of dead time in a PWM cycle of 100 xcexcs is twice the amount of the dead time. This is because a dead time is added to each side of the pulse in the PWM cycle, as shown in FIG. 1B. Thus, with 4 xcexcs out of 100 xcexcs attributed to dead time in a PWM cycle, the resulting output voltage can only be obtained from the remaining 96 xcexcs at 0.96.
The above background introduction shows that switching dead-time of solid-state power switch components, such as IGBTs, in an electronic device, such as an electronic stationary inverter, can cause output voltage distortion and voltage utilization reduction for the inverter from a direct-current (DC) power source. The inventors have found that the time delay (phase lagging) between the actual current changing polarity and the compensation voltage changing polarity is very important to effectively compensate the voltage distortion caused by the dead-time. Furthermore, not only the exact amount of voltage drop due to dead-time needs to be compensated to obtain high quality power, but also the voltage drop needs to be compensated at the right moment.
Accordingly, the preferred embodiments of the present invention provides a system and method of xe2x80x9cquadrant PWM cycle samplingxe2x80x9d to compensate the dead-time of solid-state power switch components such as IGBTs.
The preferred embodiments of the present invention also provide a system and method for shortening the compensation delay time from the moment when the output current of a power converter changes its polarity to minimize the voltage distortion around the time point of current polarity change.
The preferred embodiments of the present invention also provide a system and method of xe2x80x9cnarrow pulse eliminationxe2x80x9d to expand the voltage utilization range for solid-switch power converters with certain DC voltage.
The preferred embodiments of the present invention also provide a system and method for improving the power quality supplied from solid-switch power converters and increasing the output AC voltage magnitude range of such power converters.
Additional aspects and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the disclosure.